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ADV7800
Data Sheet
Pin No.
80
81
83
84, 87
85, 89, 99, 100, 104
86, 88
Mnemonic
XTAL
XTAL1
RESET
PVDD
AGND
ELPF1, ELPF2
Type 1
I
O
I
P
GND
I
Description
Crystal Input. Input pin for 28.63636 MHz crystal.
Crystal Output. This pin should be connected to the 28.63636 MHz crystal.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7800 circuitry.
PLL Supply Voltage (1.8 V).
Analog Ground.
External Loop Filter. The recommend external loop filter must be connected
to each ELPF pin (see Figure 8).
90
91
92
93 to 98, 110 to 115
101, 105
102
103
106
107
108, 109
116
117
118
FB
SOY
SOG
AIN1 to AIN12
AVDD
REFOUT
CML
BIAS
CAPY1
CAPC1, CAPC2
AOUT
FUNCT1
HS_IN1
I
I
I
I
P
O
O
O
I
I
O
I
I
SCART Fast Blank Input.
Sync On Luma Input. Used in embedded synchronization mode.
Sync On Green Input. Used in embedded synchronization mode.
Analog Video Input Channels. See Figure 7 for details on pin mapping.
Analog Supply Voltage (3.3 V).
Internal Voltage Reference Output.
Common-Mode Level Pin Used for the Internal ADCs.
External Bias Setting Pin. Connect the recommended resistor (1.35 k?)
between the pin and ground.
ADC Capacitor Network.
ADC Capacitor Network.
Analog Monitor Output.
SCART Function Select Input.
Horizontal Synchronization Input Signal. Used in CP mode for 5-wire
timing mode.
119
HS_IN2
I/O
Horizontal Synchronization Input Signal. Used in 24-bit digital input mode
port mode (for example, processing 24-bit RGB data from an HDMI Rx IC).
HS_IN2 in conjunction with VS_IN2 can be configured as a fast I 2 C interface
for teletext data extraction. HS_IN2 is used as the I 2 C port serial clock input.
120
ALSB
I
ALSB selects the I 2 C address for the ADV7800 control. ALSB set to Logic 0
configures the address for a write to the input/output port of 0x40. ALSB
set to Logic 1 configures the address for a write to the input/output port of
0x42.
121
122
123
SDA
SCLK
INT
I/O
I
O
I 2 C Port Serial Data Input/Output Pin.
I 2 C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).
Interrupt Output. This pin can be active low or active high. When SDP/CP
status bits change, this pin triggers. The set of events that triggers an
interrupt is under user control.
124
VS_IN2
I/O
Vertical Synchronization Input Signal. Used in 24-bit digital input mode (for
example, processing 24-bit RGB data from an DVI/HDMI Rx IC). VS_IN2 in
conjunction with HS_IN2 can be configured as a fast I 2 C interface for
teletext data extraction. VS_IN2 is used as the I 2 C port serial data
input/output pins.
125
126
127 to 136, 139 to 142, 145
VS_IN1
DE_IN
P30 to P53
I
I
I/O
Vertical Synchronization Input Signal.
Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from an DVI/HDMI Rx IC).
Video Pixel Input/Output Port. See Figure 7 for details on pin mapping.
to 154
1
GND = ground, I = input, I/O = input/output, O = output, P = power.
Rev. C | Page 12 of 28
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